The present invention relates to the field of integrated circuits, and more specifically to techniques to effectively provide greater number of external pins for input and output of data.
Semiconductor technology continues to improve. This technology allows greater and greater functionality to be provided by a single integrated circuit or xe2x80x9cchip.xe2x80x9d Signals are input to and output from the chip using external pins or pads. The chip interfaces to external circuitry, possibly on other chips, using the external pins.
The performance of a system depends in part on the amount or rate at which data can be transferred on and off the chip. This transfer rate may be referred to as the data bandwidth. One technique for increasing system performance is to provide more rapid transfer rates. This may be accomplished by improvements in process technology or circuit design. Another technique to increase system performance is to transfer a greater amount of data at one time (or xe2x80x9cin parallelxe2x80x9d). Therefore, for greater performance, it is important there are many external pins available for input and output of user data.
In an integrated circuit, certain pins are sometimes dedicated to functions other than user data I/O. For example, in a programmable integrated circuit such as a PLD or FPGA, some pins may be dedicated to the programming and testing (such as JTAG boundary scan testing) of the device. These dedicated external pin reduce the number of pins available for user I/O. The performance of the chip may be detrimentally affected since not as many user I/O signals may be transferred in parallel.
Consequently, there is a need for techniques of effectively providing greater number of external pins for input and output to obtain higher performance. Specifically, there is a need for techniques to reduce the number of external pins dedicated to functions other than user I/O, which would make greater number of external pins available for the input and output of user data.
The present invention is a technique to provide higher system performance by increasing the amount of data that may be transferred in parallel by increasing the number of external pins available for the input and output of user data (user I/O). One technique is to reduce the number of dedicated pins used for functions other than user I/O, leaving more external pins available for user I/O. The dedicated pins used to implement a function such as the JTAG boundary scan architecture may be also be used to provide other functionality, such as to select the programming modes. In a specific embodiment, a JTAG instruction code that is not already used for a JTAG boundary scan instruction may be used to replace the programming mode select pins in a programmable logic device (PLD).
In a technique of the present invention, the JTAG instruction used to replace the mode pins is shifted into a JTAG instruction register as are regular JTAG instructions. A JTAG boundary scan control logic block generates control signals to a programming mode de-coder. Based on the instruction, the programming mode decoder selects the proper programming mode, and generates the appropriate programming mode signals. The programming mode signals are provided to the programming circuitry, and integrated circuit will be appropriately configured.
In a specific implementation, each single bit of the JTAG instruction code may be used to replace one programming mode select pin. In another implementation, the whole JTAG instruction code may be used to replace one mode select pin after instruction decoding. Technically, by doing this, many, or all, the mode pins can be eliminated, thus increasing the number of total available I/O pins. This concept provides advantages compared to JTAG programming and in-system programming (ISP) in such a way that a PLD device may be configured for different modes including test, scan, and programming modes.
The advantages of using JTAG instructions to replace programming the mode select pins of a programmable integrated circuit include saving device package costs and leaving space for more user I/Os. Overall, this increases the available functionality and value of the devices. There is relatively little cost to implement the circuits to implement PLD programming mode selection with JTAG circuits.
In a specific embodiment, the present invention is a method of configuring a programmable integrated circuit. An instruction is provided to a JTAG instruction register. The instruction is passed to a JTAG boundary scan control logic block. The JTAG boundary scan control logic block generates a control signal. The control signal is passed to a programming mode decoder. Based on the control signal, a programming mode signal is generated to place the programmable integrated circuit in a configuration mode.
Further, the present invention is a programmable integrated circuit including a JTAG state machine; an instruction register coupled to the JTAG state machine; a JTAG boundary scan control logic block coupled to the instruction register; and a programming mode decoder coupled to receive a mode signal from the JTAG boundary scan control logic block.
Another aspect of the present invention includes the use of JTAG circuitry resident on a programmable integrated circuit to select a programming mode of the integrated circuit. Further, the present invention includes the use of an instruction input to a JTAG instruction register, where this instruction is not used to perform a IEEE 1149.1 standard function, to place a programmable integrated circuit into a specific programming mode identified by the instruction. A still further aspect of the present invention is the use of JTAG circuits on a programmable logic device to place the programmable logic device in a configuration mode.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.